NASA, Purdue launch center to create next-generation computers

WEST LAFAYETTE, Ind. – Future NASA spacecraft will need to think for themselves.

To help create the brains for these ships – a new generation of compact, high-performance computers – scientists, engineers and officials from state and federal agencies met today (Wednesday, 1/15) at Purdue University. Their mission: to kick off a new NASA Institute for Nanoelectronics and Computing, a collaboration of six universities led by Purdue.
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"Innovative technologies developed under the auspices of the institute will benefit the U.S. space program for decades to come," said Purdue President Martin C. Jischke. "The research also will benefit Indiana and society in general through possible technology spinoffs, and it will provide learning opportunities for our best students, who represent the coming generation of scientists and engineers."

Researchers will hold a series of meetings about the institute during three days of talks that began with a luncheon from 11:30 a.m. to 1 p.m. today in the Purdue Memorial Union North Ballroom. The luncheon was organized to formally announce the new institute, and researchers also will be discussing another new federally funded nanotechnology effort during the meetings, which will continue until 12:30 p.m. Friday (1/17).

The institute will receive $15 million from the National Aeronautics and Space Administration – $3 million annually over five years – and $2 million over five years from the Indiana 21st Century Research and Technology Fund. The fund, established by the state to promote high-tech research and development and to help commercialize university research, provided critical funding for an earlier center at Purdue that set the stage for the NASA institute and other nanotechnology efforts.

"The team based at Purdue will be looking at several novel, unconventional technologies," said Meyya Meyyappan, director of the Center for Nanotechnology at the NASA Ames Research Center, in Moffett Field, Calif. "These technologies will have applications for military and commercial systems as well."

The institute will be headquartered at Purdue's Birck Nanotechnology Center, one of four centers that will be part of the university's recently created Discovery Park. The park will be a complex of facilities that use a multidisciplinary approach to develop new technologies.

Future computers will make spacecraft more autonomous so they can better function in remote regions of space without the need for human intervention, said Supriyo Datta, director of the institute and Purdue's Thomas Duncan Distinguished Professor of Electrical and Computer Engineering.

"The research will focus on improving the electronics for NASA space missions, which require lots of computation, sensing, data collection, storage and communication," Datta said. "The system has to be able to respond to unexpected circumstances.

"You don't know what you are going to encounter on a space mission."


The brains of these future spacecraft will be miniature supercomputers.

"For all decisions to be made right at the spacecraft, instead of at mission control here on Earth, requires enormous computing power, orders of magnitude more than what we have today," Meyyappan said. "These computers will have to come in small packages because you can't haul a bunch of mainframes into space."

Purdue will work with researchers at Northwestern, Cornell and Yale universities, the University of Florida and the University of California at San Diego.

Industry may soon be able to fit more than 1 billion transistors on a computer chip about 2 centimeters square. Current chips contain about 350 million transistors. The feat of cramming more and more transistors onto a chip is largely accomplished by shrinking critical components in the transistors, electrodes known as gates. Gate lengths soon will be shrunk to about 10 nanometers, compared to about 65 nanometers for gate lengths in conventional transistors.

One nanometer is about the length of 10 atoms strung together.

The 10-nanometer milestone, however, may represent the limit to how small transistors can be made. For various reasons, it will no longer be economically practical to shrink transistors any smaller or to fit more transistors onto a silicon chip.

"That means the only way to make progress after that is to start using the third dimension, to start stacking layers on top of each other," said Mark Lundstrom, Purdue's Scifres Distinguished Professor of Electrical and Computer Engineering, whose work includes research in nanotechnology.

The first layer of these three-dimensional chips will be similar to today's chips but will probably contain between 1 to 10 billion transistors.

"The bottom layer will generally perform the same functions performed by digital equipment – things like digital processing in your computer or digital signal processing in your wireless phone," Datta said. "The layers on the top of that first layer will probably add different kinds of capabilities."

These new capabilities may include "ultradense memory" many times greater than the memory in current chips, sensors and pattern-recognition devices for artificial intelligence functions such as navigation, image analysis and the search for living organisms in space.

Perhaps these additional layers will contain innovative devices made not out of silicon but out of organic molecules, such as proteins or exotic structures called carbon nanotubes, Datta said.

The first, more conventional silicon layer may serve as a template on which to "grow" subsequent layers that may "self-assemble," similar to the growth of structures in living organisms. In this case, devices would eventually be fabricated using techniques based on chemical attractions, rather than the complex processes now used to etch electronic circuits. Producing smaller and smaller silicon devices will increase manufacturing costs, but self-assembly would make electronics processing far less expensive than the future, projected costs of conventional processing.

"With silicon technology, you basically carve tiny structures out of a piece of silicon," Lundstrom said. "The hope is that you could self-assemble the complex structures inside future chips much more efficiently, and at less expense than is possible with current chip-processing methods."

Future chips will operate much faster than conventional chips. At the same time, the chips will have to consume far less electricity than conventional circuits – perhaps needing only one-tenth the power of today's computers, making it possible to build super-powerful computers that don't use as much electricity as present-day supercomputers. The low-power computers also will need to have novel designs that produce less heat than their conventional counterparts.

"Heat is a critical problem," Datta said. "If each transistor generates a nanowatt of power and you put billions of them in this small volume, it will heat up too much and essentially destroy the chip."

The institute is one of seven new University Research, Engineering and Technology Institutes created by NASA and the U.S. Department of Defense.

Lundstrom is leading another new nanotechnology center at Purdue, the Network for Computational Nanotechnology, which also is being kicked off during the three days of talks at Purdue. That center is a group of seven universities: Purdue, the University of Illinois, the University of Florida, Northwestern University, Stanford University, Morgan State University and the University of Texas, El Paso. Funded with a five-year, $10.5 million grant from the National Science Foundation, the center will develop and use computer simulations needed to design devices for a wide range of applications in nanotechnology.

"These two federally funded centers complement each other," Lundstrom said. "They address similar problems, but the NASA institute focuses on experimental work and the NSF network focuses on theory and computation."

Both the NASA institute and the NSF center will be based at Discovery Park, which will contain four major facilities: the Birck Nanotechnology Center, the Bindley Bioscience Center, the Burton D. Morgan Center for Entrepreneurship and an e-enterprise center.

"The early success of Discovery Park has been very impressive," said Charles O. Rutledge, the park's executive director and interim vice provost for research.

Since plans for the park were first announced in September 2001 it has attracted $48.7 million in research funding from state, federal and private sources. In addition to that funding, the Lilly Endowment has given nearly $26 million toward start-up costs, $2 million of which has recently been used to recruit 10 top scientists and engineers to work in the park, Rutledge said.

"This money has helped us attract the very best scientists and engineers," Rutledge said. "These are highly qualified people who will be faculty members and researchers within the Schools of Engineering and the School of Science, while also working at Discovery Park."

Work has begun on the construction site for the Burton D. Morgan Center for Entrepreneurship, which is expected to be completed in early 2004. The Birck Nanotechnology and Bindley Bioscience centers are expected to be completed in 2005, and the construction schedule for the e-enterprise center has not yet been determined.

The Birck center will contain laboratories designed specifically for research in nanotechnology, an emerging science in which new materials and tiny structures are built atom-by-atom or molecule-by-molecule. "Nano" is a prefix meaning one-billionth, so a nanometer is one-billionth of a meter.

Keynote Speaker 3

Engineering of Nanowire Heterostructures Harry E. RUDA
Energenius Professor of Advanced Nanotechnology Centre for Advanced Nanotechnology University of Toronto, Canada

Harry Ruda received the B.Sc. degree in materials physics with honors from Imperial College, London University, England, in 1979, and the Ph.D. degree from Massachusets Institute of Technology, Cambridge, Massachusets, USA, in 1982, for work on growth and characterization of HgCdTe for infrared detectors. Following these studies, he accepted an IBM postdoctoral fellowship to work on defect calculations in GaAs and transport in low dimensional GaAlAs-based quantum heterostructures. In 1984 he joined 3M where his work focused on theoretical optical and transport properties of wide bandgap II-VI semiconductors, principally ZnSe-based. In 1989, Dr. Ruda joined the University of Toronto and now holds the position of Full Professor. He currently is also the Energenius Advanced Nanotechnology chair holder, and director of the Energenius Centre for Advanced Nanotechnology.

Keynote Speaker 2

Nanotubes: Large-scale Production and their Practical Applications Endo MORINOBU
Professor Shinshu University, Japan

Dr. Morinobu Endo is Professor of Shinshu University. His current work ranges from basic science to applications of various forms of carbons; carbon nanotubes, new forms of carbon and graphite, nano-porous carbons,graphite intercalation compounds, Li ion battery, electric double layer capacitors. After receiving a M.S. degree from Shinshu University, he obtained a Ph.D. from Nagoya University. He is the present chairman of Japan Carbon Society, and he was one of the group chairmen of Industry-University Cooperative Research Committees, No.117 JSPS (Japanese Society for Promotion of Science). He also is one of the international advisory members of CARBON journal. He has been invited at many international conferences and symposium as a plenary lecturer/key-note speaker. In addition, he has joined many international conferences as a chairman, organizer and advisory board member.

Keynote Speakers

Field-Effect Transistor Theory (A Summary of Recent Advances) Chih-Tang SAH
Professor of Physics and Professor of Electrical Engineering Univesity of Florida, Gainesville, USA

Chih-Tang Sah received the BS degrees in Physics (1953) and in Electrical Engineering (1953) from the University of Illinois in Urbana-Champaign, and the MS (1954) and PhD (1956) degrees from Stanford. He apprenticed with Shockley (1956-1959) and joined Fairchild Semiconductor Corporation (1959-1964) where he helped hire, direct and manage the 64-member Fairchild Physics department which was responsible in the development of the first generation manufacturing technologies for volume production of silicon bipolar and MOS transistors and integrated circuits. He was appointed a professor of physics and a professor of electrical engineering at the University of Illinois in Urbana-Champaign (UIUC) for 25 years (1962-1988) and an Eminent Scholar and a Graduate Research Professor at the University of Florida (UFL) for 20 years (1988-2008) which is continuing. He wrote a three-volume textbook titled Fundamentals of Solid-State Electronics (1991 FSSE) , FSSE- Study Guide (1993) and FSSE- Solution Manual (1996), the latter included a 100-page exposition on Transistor Reliability. FSSE was translated into Chinese (2003). He was the Founding Editor (1991) of the International Series on the Advances in Solid State Electronics and Technology (ASSET) which published three titles by invited authors (1990's) and is currently publishing six monographs (2007-8) by invited authors on compact modeling of devices for computer-aided design of integrated circuits, all with the World Scientific Publication Company. He was named a world's 1000 most cited scientist during 1963 to 1978 by the Institute of Scientific Information. He is a Life Fellow of the IEEE, the American Physical Society and the Franklin Institute, and a Fellow of American Association of the Advancement of Science. Dr. Sah was appointed an Honorary Professor of Peking (2002), Tsinghua (2003) and Xiamen (2004) Universities of China and received the Doctorem Honoris Causa from the Katholiche Universteit de Leuven, Belgium (1975) and the Honorary Doctorate from Chiaotung University, Taiwan (2004). His semiconductor research and teaching contributions were recognized thrice by the IRE-IEEE: the Browder J. Thompson Prize (IRE-1962) for the best paper published by an author under thirty, and the IEEE J. J. Ebers (1981) and Jack Morton (1989) Awards; twice by the semiconductor industry, the co-recipient with Morris Chang the First Achievement Award in High Technology of the Asian-American Manufacturing Association in San Jose, California (1984), and the Fourth annual University Research Award of the Semiconductor Industry Association (1998). He was the co-recipient in integrated circuit technology, with Yung-Cheng Fung in bioengineering, of the first Pioneer Recognition Award of the Committee-of-100 (a Chinese-American-citizen organization). He was the second annual Distinguished Lifetime Achievement Award of the Asian-American Engineer of the Year sponsored by the Chinese Institute of Engineerings/USA (2003). Professor Sah was elected an Academician of the US National Academy of Engineering (1986), the Academia Sinica in Taipei (1998) and the Chinese Academy of Sciences in Beijing (2000). His current research has been on MOS transistor models in order to help further the development of compact models for computer aided design of nanometer MOS integrated circuits.

EMC Posts Earnings Jump, But VMware Disappoints

EMC beats Wall Street expectations with a 33 percent rise in earnings, but the storage technology company's euphora was short-lived as its VMware unit failed to meet the street's expectation despite an 80 percent rise in sales. EMC expects VMware to contribute to its earnings this year.

EMC posted robust earnings of $525.7 million for the fourth quarter -- a 33 percent rise over year-earlier results that beat Wall Street's expectations. Moreover, revenue increased by 19 percent to a record $3.83 billion.

Despite troubling signs of deteriorating U.S. economic conditions, EMC saw its revenue rise by a healthy 16 percent in North America, which represented 55 percent of the company's total revenue in the quarter. Even better, EMC's revenue growth from operations overseas increased by 23 percent, on average, in comparison with the year-ago quarter.

EMC Chief Executive Joe Tucci characterized all of 2007 as a breakout year for the company. "We exceeded all of the aggressive financial targets we set out to achieve at the beginning of the year," he said.

Caution Rules the Day

EMC's information-storage unit increased its fourth-quarter revenue by 14 percent to $3.03 billion due to strong customer demand for IP storage solutions and next-generation backup and recovery capabilities. Moreover, the company's content management and archiving unit grew revenue by 17 percent to $238 million, in comparison with year-earlier results. Additionally, EMC's revenue at its RSA information-security Relevant Products/Services unit grew by 30 percent year-over-year to $148 million.

Looking forward, CFO David Goulden said EMC has never been better positioned to continue to grow and gain market share. At the same time, however, Tucci admitted that the current economic climate is both "more challenging and more uncertain" than in 2007.

"We have not seen much on the downside, but moving forward, being cautious is the rule of the day," Tucci told analysts during a conference call.

Tucci expects IT spending growth to continue but "at a couple of points less than in 2007." On the bright side, Tucci noted that the key IT segments of information storage, content management and archiving, and information security are forecast to grow by 5, 8 and 16 percent, respectively, during 2008.

"EMC is well positioned in the areas where IT spending will grow the fastest this year," Tucci said. "And we are expanding our global presence with commercial customers in key emerging markets."

Tucci expects his company's 'One EMC' initiative "to interlock and drive more technology and product integrations across our information storage, content management and archiving, and RSA information security business units, making it much easier for our customers and partners to do business with EMC." He also predicted that flash drive technology will "revolutionize the storage industry over the next several years."

VMware Disappoints

Tucci credited EMC's highly successful partial IPO of VMware as one way that the company had met its key 2007 goals. Going forward, VMware's contribution to EMC's bottom line will continue, given that the parent holds 85 percent of the spin-off's shares.

Though VMware reported an 80 percent rise in sales to $412 million in the fourth quarter, the result failed to fulfill Wall Street's expectation of $417 million. Moreover, the entry of Microsoft Relevant Products/Services into the virtualization software arena later this year raises doubts about VMware's prospects in 2008. Industry analysts estimate that VMware accounted for about 13 percent of EMC's revenues last year.

"As others begin to enter the market, VMware and our partners are continuing to broaden and deepen our highly reliable end-to-end virtualization solutions," VMware CEO Diane Greene told investors during a conference call.

Meanwhile EMC intends to continue to focus on innovation and research and development. The effort is expected to enable the company "to tackle emerging customer priorities such as Web 2.0, virtualization, compliance and new online methods for purchasing and consuming software," Tucci said.

About this project


This exploratory project pushes the limits of current photonic technology.
The ultimate goal of this project is to develop a technology for on-chip integration of ultra-compact nanophotonic circuits for manipulating the light signals, similar to the way electrical signals are manipulated in computer chips.

Integration of optical devices at the chip scale is seen as key to significantly reducing the cost of optical components. Dense photonic integration therefore might enable the whole new area of optical interconnects to be economically viable at different length scales in the systems, between the boards, on the cards and may be eventually even on a computer chip.
The important part of this project is to design and test nanophotonic circuits, which can leverage IBM's expertise in microelectronic circuit fabrication. Eventually the development of the nanophotonic technology compatible with CMOS fabrication line could result in cheap mass production of densely integrated optoelectronic superchips comprising both photonic and electronic circuitry.


Futuristic silicon chip with monolithically integrated photonic and electronic circuits
This hypothetic chip performs all-optical routing of mutliple N optical channels each supporting 10Gbps data stream. N channels are first demultiplexed in WDM photonic circuit, then rearranged and switched in optical cross-connect OXC module, and multiplexed back into another fiber with new headers in WDM multiplexer. Data packets are buffered in optical delay line if necessary. Channels are monitored with integrated Ge photodetector PD. CMOS logical circuits (VLSI) monitor the performance. Electrical pads are connecting the optoelectronic chip to other chips on a board via electrical signals.


Silicon or more specifically silicon-on-insulator (SOI) is an attractive platform for photonic integration owing to its high refractive index that offers strong light confinement and therefore ultra-compact devices. On the other hand by adopting a substrate material that is CMOS compatible, decades of materials and process knowledge can be leveraged. Feasibly both passive and active optical elements could be combined with electronics on a single chip to achieve monolithic optoelectronic integration.

Nanotechnology & Nanoscience

Research Area

IBM's nanotechnology research aims to devise new atomic- and molecular-scale structures and devices for enhancing information technologies, as well as discover and understand their scientific foundations.

Leading the development of nanotechnology, IBM's scientists have made numerous breakthroughs in the study of these nano-scale technologies.

In particular, carbon nanotubes and scanning probes derived from the atomic force microscope -- cousin of the scanning tunneling microscope -- show particular promise in enabling dramatically improved circuits and data storage devices. Research on nanoparticles leads to applications in biomedicine as well as hard disk drive storage. Photonic bandgap materials -- on-chip nanoscale structures the size of a wavelength of light -- will manipulate light as optical waveguides, splitters and routers. Research into nanomechanical information storage, such as IBM's Millipede project, continues to increase the possibilities for increased areal storage density.

IBM's research into nano-scale structures that self-assemble may one day obviate the need to "hand-position" atoms. Nanotechnology will allow the design and control of the structure of an object on all length scales, from the atomic to the macroscopic enabling more efficient and vastly less expensive manufacturing processes and providing the hardware foundation for future information technology.